Call for Papers

Important dates



First Workshop on Composable Systems (COMPSYS ‘22)

Paul Carpenter Barcelona Supercomputing Center

Paul Carpenter is Senior Researcher and Ramon y Cajal fellow at Barcelona Supercomputing Center (BSC), where he is Principal Investigator for the EuroEXA and ExaNoDe projects. He graduated in BA Mathematics (1997) and Diploma in Computer Science (1998) from the University of Cambridge, and received his PhD in computer architecture from the Technical University of Catalonia in 2011. Prior to starting his PhD, he was Senior Software Engineer at ARM in Cambridge, UK, where he was technical lead for audio/video codec development. As independent consultant to ARM he was part of the small team that designed the ARM Advanced SIMD (NEON) vector ISA. He is Software Technical Manager for EuroEXA, co-chair of ETP4HPC’s Working Group on Programming Environment and was co-editor of the EuroLab-4-HPC Long-Term Vision on High-Performance Computing. His primary research interests are resource management, performance-portable parallel programming models and runtime systems.

Allan J. Cantle CEO, Nallasway Inc.

Allan Cantle is CEO of Nallasway, consulting on Heterogeneous, High Performance Computing Solutions. He is currently contracting with the OpenCAPI Consortium as the Technical Director and Board Advisor. He also volunteers as the Technical Lead for the OCP HPC SubProject. Previously, Allan was the founder of Nallatech, which, during his 25 year tenure, became widely known as a pioneer in FPGA Accelerated Computing. Before founding Nallatech; Allan was an Electronics Systems Engineer at BAE systems, developing real-time heterogeneous high-performance computers. He holds a BEng degree in Electrical and Electronics Engineering from the University of Plymouth and an MSc in Corporate Leadership.

Sudhanva Gurumurthi AMD

Sudhanva Gurumurthi is a Principal Member of the Technical Staff at AMD, where he leads advanced development in Reliability, Availability, and Serviceability (RAS). His responsibilities include leading the pathfinding of new RAS features and its technology transfer into the company roadmap, leading the definition of new technologies and capabilities in industry consortiums, and providing guidance on emerging technologies and use cases to R&D teams. His recent industry contributions include leading the ECC definition for JEDEC HBM3 DRAM and error logging and signaling enhancements for CXL 2.0 memory devices. Additionally, he serves on the Dean’s Advisory Council of the College of Science and Engineering at Texas State University. Prior to joining industry, Sudhanva was an Associate Professor with tenure in the Computer Science Department at the University of Virginia. He is a recipient of an NSF CAREER Award, a Google Focused Research Award, an IEEE Computer Society Distinguished Contributor recognition, and several other awards and recognitions. Sudhanva regularly serves on the program and organizing committees of major computer architecture conferences and has served as an editor for IEEE Micro Top Picks, IEEE Computer Architecture Letters, and IEEE Transactions on Computers. He received his PhD in Computer Science and Engineering from Penn State in 2005.

Charles Johns IBM

Charles Johns is a STSM in the IBM Research. Mr. Johns received his B.S. degree in Electrical Engineering from the University of Texas at Austin in 1984. After joining IBM Austin in 1984, Mr. Johns worked on various disk, memory, voice communication, and graphics adapters for the IBM Personal Computer. From 1988 until 2000, he was part of the Graphics Organization and was responsible for the architecture and development of entry and midrange 3-D graphics adapters and GPUs. From 2000 to 2010, Mr. Johns was part of the STI Project responsible for the Cell Broadband Engine Architecture (CBEA) and participated in the development of the Cell Broadband Engine (CBE; the first implementation of the CBEA). After the Cell program, Mr. Johns worked on various High-Performance Computing and Cloud Computing solutions. Mr. Johns was the primary architect of the Coherent Accelerator Processor Interface (CAPI) for the POWER processors. Mr. Johns is currently working on Future of Computing system architectures. He has a broad knowledge of system and chip design, and the ability to lead diverse teams in the development of advanced computer systems. He is an IBM Master Inventor with over 100 patents.